This invention is concerned with techniques for ensuring uniform threshold voltages among multiple field effect transistors (FETs) fabricated on different III-V compound semi-insulating wafers or in different processing lots.
III-V compound integrated circuit technology has matured rapidly, demonstrating large scale (LSI) complexity, gigabit clock rates, and a radiation hardness which surpasses that of silicon-based circuits. This advanced digital circuit technology is based upon the unique high electron mobility and semi-insulating properties of III-V materials. The capability of producing manufacturing quantities of high quality III-V integrated circuits, however, depends on the development of acceptable manufacturing circuit design rules, manufacturing approaches, and process controls.
In LSI and VLSI (very large scale) integrated circuits, the uniformity and reproducibility of FET threshold voltages is critical to successful production and operation. In the manufacturing environment, the threshold voltage should not vary among depletion mode (normally on) devices by more than 100 mV. The requirement is even more stringent for enhancement mode (normally off) logic, in which the threshold voltage variation cannot exceed 50 mV from wafer to wafer. The threshold voltage of a field effect transistor is controlled by the impurity profile which results following ion implantation and annealing. Changing the implant energy and dose changes the distribution and magnitude of the donor profile and, hence, the threshold voltage of the FET. Due to variations in the starting materials and in the prior art processes which are used, GaAs (gallium arsenide) FET threshold voltage variations from wafer to wafer often exceed the acceptable limits, leading to reduced device yields and higher production costs.
The most common method which has been used in the prior art to adjust threshold voltages is to fabricate a recessed-gate device. In this approach, the III-V wafer surface is etched in the channel area of a FET prior to applying the gate metallization. The consequent removal of charge carriers in the etched material shifts the threshold voltage. The drain-source current for the FET is monitored during the etching process to detect the point when the proper threshold is reached. This method has also been used in producing enhancement mode devices. The etching method, however, is time consuming and thus not suitable for a manufacturing environment. In addition, this method is not sufficiently controllable, particularly if a wet chemical etch is used to form the recess.